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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16335
96-Bit AC-PDP DRIVER
The PD16335 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It consists of a 96-bit bi-directional shift register, 96-bit latch and high-voltage CMOS driver. The logic block is designed to operate using a 5-V power supply enabling direct connection to a gate array or a microcontroller. In addition, the
PD16335 achieves low power dissipation by employing CMOS structure while having a high withstand voltage output
(80 V, +50/-75 mA).
FEATURES
* Selectable by IBS pin; three 32-bit bi-directional shift register circuits configuration or six 16-bit bi-directional shift register circuits configuration * Data control with transfer clock (external) and latch * High-speed data transfer (fmax. = 25 MHz min. at data fetch) (fmax. = 16 MHz min. at cascade connection) * High withstand output voltage (80 V, +50/-75 mAMAX.) * 5 V CMOS input interface * High withstand voltage CMOS structure * Capable of reversing all driver outputs by PC pin
ORDERING INFORMATION
Part Number Package COBNote
PD16335
Note Please consult with an NEC sales representative about COB.
Document No. S12192EJ2V0DS00 (2nd edition) Date Published May 1998 N CP(K) Printed in Japan
(c)
1998
PD16335
BLOCK DIAGRAM (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER)
OE PC BLK VDD2 LE
SR1 A1 CLK R/L B1 A1 CLK R/L B1 S1 S4 . . . . . . . . . . . . . . . . S94 S1 S2 S3 L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O96
VSS2
SR2 A2 A2 CLK R/L B2 B2 S2 S5 . . . . . . . . . . . . . . . . S95
SR3 A3 A3 CLK R/L B3 B3 S3 S6 . . . . . . . . . . . . . . . . S96
VDD2
S94 S95 S96
SRn: 32-bit shift register VSS2
2
PD16335
BLOCK DIAGRAM (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER)
OE PC BLK VDD2 LE SR1 A1 S1 CLK S7 . . . R/L S91 B1 SR2 A2 S2 CLK S8 . . . R/L S92 B2 SR3 A3 S3 CLK S9 . . . R/L S93 B3 SR4 A4 S4 CLK S10 . . . R/L S94 B4 SR5 A5 S5 CLK S11 . . . R/L S95 B5 SR6 A6 S6 CLK S12 . . . R/L S96 B6 SRn: 16-bit shift register VSS2
A1 CLK R/L B1 A2
B2 A3
B3 A4
B4 A5
B5 A6
B6
S1 LE S2 S3 S4 S5 S6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S93 S94 S95 S96
L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS2
VDD2
O1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O96
3
PD16335
PIN DESCRIPTION
Symbol PC BLK LE OE A1 to A3 (6) B1 to B3 (6) CLK R/L Blank input Latch enable input Output enable RIGHT data input/outputNote Pin Name Polarity change input Description PC = L: All driver output invert BLK = H: All output = H or L Data latch by rising edge of this signal. Make output high impedance by input H When R/L = H (values in parentheses are for 6-bit input) A1 to A3 (6): Input B1 to B3 (6): Output When R/L = L (values in parentheses are for 6-bit input) A1 to A3 (6): Output B1 to B3 (6): Input Shift executed on fall Right shift mode when R/L = H SR1: A1 S1 *** S94 B1 (Same direction for SR2 to SR6) Left shift mode when R/L = L SR1: B1 S94 *** S1 A1 (Same direction for SR2 to SR6) H: 32-bit length shift register, 3-bit input L: 16-bit length shift register, 6-bit input 80 V, +50/-75 mA 5 V 10% 10 to 70 V Connect to system GND Connect to system GND
MAX.
LEFT data input/outputNote Clock input Shift control input
IBS O1 to O96 VDD1 VDD2 VSS1 VSS2
Input mode switch High withstand voltage output Power supply for logic block Power supply for driver block Logic GND Driver GND
Note When input mode is 3-bit, set unused input and output pins "L" level.
TRUTH TABLE 1 (Shift Register Block)
Input R/L H H L L CLK H or L H or L OutputNote 2 Output Input A Output B OutputNote 1 Output Input Right shift execution Hold Left shift execution Hold Shift Register
Notes 1. The data of S91 to S93 (S85 to S90) shifts to S94 to S96 (S91 to S96) and is output from B1 to B3 (B1 to B6) at the falling edge of the clock, respectively. (Values in parentheses are for 6-bit input) 2. The data of S4 to S6 (S7 to S12) shifts to S1 to S3 (S1 to S6) and is output from A1 to A3 (A1 to A6) at the falling edge of the clock, respectively (Values in parentheses are for 6-bit input)
TRUTH TABLE 2 (Latch Block)
LE H or L Output State of Latch Block (Ln) Latch Sn data Hold latch data
TRUTH TABLE 3 (Driver Block)
Ln X X X X X BLK H H L L X PC H L H L X OE L L L L H Output State of Driver Block H (All driver outputs: H) L (All driver outputs: L) Output latch data (Ln) Output inverted latch data (Ln) Set output impedance high
4
X: H or L, H: High level, L: Low level
PD16335
TIMING CHART (WHEN IBS = "H": 3-BIT INPUT, RIGHT SHIFT)
Values in parentheses in the following chart are when R/L = L.
CLK A1 (B3) A2 (B2) A3 (B1)
S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91)
LE BLK PC OE
Latch by rising edge
High impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91)
5
PD16335
TIMING CHART (WHEN IBS = "L": 6-BIT INPUT, RIGHT SHIFT)
Values in parentheses in the following chart are when R/L = L.
CLK A1 (B6) A2 (B5) A3 (B4) A4 (B3) A5 (B2) A6 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) S7 (S90) LE BLK PC OE High impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) O7 (O90) Latch by rising edge
6
PD16335
ABSOLUTE MAXIMUM RATINGS (TA = 25C, VSS1 = VSS2 = 0 V)
Parameter Logic Block Supply Voltage Driver Block Supply Voltage Logic Block Input Voltage Driver Block Output Current Junction Temperature Storage Temperature Symbol VDD1 VDD2 VI IO2 Tj Tstg. Ratings -0.5 to +7.0 -0.5 to +80 -0.5 to VDD1 +0.5 +50/-75 125 -65 to +150 Unit V V V mA C C
RECOMMENDED OPERATING CONDITIONS (TA = -40 to +85C, VSS1 = VSS2 = 0 V)
Parameter Logic Block Supply Voltage Driver Block Supply Voltage High-Level Input Voltage Low-Level Input Voltage Driver Output Current Symbol VDD1 VDD2 VIH VIL IOH2 IOL2 MIN. 4.5 10 0.7 VDD1 0 TYP. 5.0 MAX. 5.5 70 VDD1 0.2 VDD1 -60 +40 Unit V V V V mA mA
Caution In order to prevent latch-up breakage, be sure to enter the power to VDD1, logic signal and VDD2 in that order, and turn off the power in the reverse order, keep this order also during a transition period.
ELECTRICAL SPECIFICATIONS (TA = 25C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V)
Parameter High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Symbol VOH1 VOL1 VOH21 VOH22 Low-Level Output Voltage VOL21 VOL22 Input Leakage Current High-Level Input Voltage Low-Level Input Voltage Static Current Dissipation IIL VIH VIL IDD1 IDD1 IDD2 IDD2 Logic, TA = -40 to +85 Logic, TA = 25C Driver, TA = -40 to +85 Driver, TA = 25C Conditions Logic, IOH1 = -1.0 mA Logic, IOL1 = 1.0 mA O1 to O96, IOH2 = -1.3 mA O1 to O96, IOH2 = -13 mA O1 to O96, IOL2 = 5 mA O1 to O96, IOL2 = 40 mA VI = VDD1 or VSS1 0.7 VDD1 0.2 VDD1 100 10 1000 100 MIN. 0.9 VDD1 0 69 65 1.0 10 1.0 TYP. MAX. VDD1 0.1 VDD1 Unit V V V V V V
A
V V
A A A A
7
PD16335
SWITCHING CHARACTERISTICS (TA = 25C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL = 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter Transmission Delay Time Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ tPZH tPLZ tPZL Rise Time tTLH tTLZ tTZH Fall Time tTHL tTHZ tTZL Maximum Clock Frequency fmax. O1 to O96 RL = 10 k O1 to O96 O1 to O96 RL = 10 k O1 to O96 When data is read, duty 50% cascade connection, Duty 50% Input Capacitance CI 25 16 15 OE O1 to O96 RL = 10 k PC O1 to O96 BLK O1 to O96 CLK (LE = H) O1 to O96 CLK A/B Conditions MIN. TYP. MAX. 55 55 180 180 165 165 160 160 300 180 300 180 120 3 120 150 3 150 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
s
ns ns
s
ns MHz MHz pF
TIMING REQUIREMENT (TA = -40 to +85C, VDD1 = 4.5 to 5.5 V, VSS1, 2 = 0 V, tr = tf = 6.0 ns)
Parameter Clock Pulse Width Latch Enable Pulse Width Blank Pulse Width PC Pulse Width OE Pulse Width Data Setup Time Data Hold Time Latch Enable Time 1 Latch Enable Time 2 Symbol PWCLK PWLE PWBLK PWPC PWOE tsetup thold tLE1 tLE2 RL = 10 k Condition MIN. 20 20 200 200 3.3 7 10 20 20 TYP. MAX. Unit ns ns ns ns
s
ns ns ns ns
8
PD16335
SWITCHING CHARACTERISTICS WAVEFORM
1/fmax. PWCLK (H) PWCLK (L) 3.3 V CLK 50% 50% 50% VSS1
tsetup
thold 3.3 V
An/Bn (Input)
50%
50% VSS1
tPHL1
tPLH1 VOH1
Bn/An (Output)
50%
50% VOL1
3.3 V LE 50% 50% VSS1
PWLE tLE1 tLE2 3.3 V CLK 50% 50% VSS1
tPHL2 VOH2
On
90%
VOL2
tPLH2 VOH2 On 10%
VOL2
9
PD16335
PWBLK 3.3 V BLK 50% 50% VSS1
tPHL3
tPLH3 VOH2 10%
On
90%
VOL2
PWPC 3.3 V PC 50% 50% VSS1
tPHL4
tPLH4 VOH2
On
90% 10% VOL2
PWOE 3.3 V OE 50% 50% VSS1
tPLZ
tTLZ
tPZL
tTZL VO (H)
90% On
90%
10% 10% VOL2 VOH2 90% On 10% tPHZ tTHZ 90%
10% VO (L) tPZH tTZH
10
PD16335
[MEMO]
11
PD16335
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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